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K Series with PFC Data Sheet
150 – 280 Watt AC-DC Converters
Table 21: Undervoltage monitoring functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis V ho [% of V t ]
JFET NPN
V b 4
V o / V o1
of threshold level V t
V tb 4
V to
for V t min – V t max
V ho
D1
D2
D5
D6
no
yes
yes
no
-
355 VDC
3.5 – V BR 1
-
2.5 – 0.6 V
-
D3
D4
D0
D7
D8
D9
yes
no
no
yes
yes
yes
355 VDC
-
-
(0.95 – 0.985 V o1 )
(0.95 – 0.985 V o1 )
3.5 – V BR 3
2
2
"0"
"0"
2.5 – 0.6 V
yes
yes
355 VDC
3.5 – V BR 3
2.5 – 0.6 V
DD
yes
yes
355 VDC
3.5 – V BR
1
2.5 – 0.6 V
1 Threshold
level adjustable by potentiometer. See Output Data for V BR .
2
3
4
Fixed value. Tracking if V o1 is adjusted via R-input, option P, or sense lines.
The threshold level permanently adjusted according to customer specification ±2% at 25 °C. Any value within the specified range
is basically possible, but causes a special type designation in addition to the standard option designations (D0/D9).
V b is the voltage generated by the boost regulator. When V b drops below 355 V, the D signal triggers, and the output(s) will
remain powered during nearly the full hold-up time t h .
D Undervoltage Monitor
Table 22: JFET output (D0 – D4)
The input and/or output undervoltage monitoring circuit
operates independently of the built-in input undervoltage
lockout circuit. A logic "low" (self conducting JFET) or "high"
signal (NPN output) is generated at the D output (pin 20),
when one of the monitored voltages drops below the
V b , V o1 status
V b or V o1 < V t
V b and V o1 > V t + V h
D output, V D
low, L, V D ≤ 0.4 V at I D = 2.5 mA
high, H, I D ≤ 25 μA at V D = 5.25 V
preselected threshold level V t . This signal is referenced to
S– / Vo1–. The D output recovers, when the monitored
voltages exceed V t + V h . The threshold level V bi is adjusted
in the factory. The threshold level V to is either adjusted by a
potentiometer accessible through a hole in the front cover,
or adjusted in the factory to a fixed value specified by the
customer.
Option D exists in various versions D0 – DD, as shown in
the table below.
JFET output (D0 – D4) :
Pin D is internally connected via the drain-source path of a
NPN output (D5 – DD):
Pin D is internally connected via the collector-emitter path
of a NPN transistor to the negative potential of output 1. V D
< 0.4 V (logic low) corresponds to a monitored voltage
level ( V i and/or V o1 ) > V t + V h . The current I D through the
open collector should not exceed 20 mA. The NPN output
is not protected against external overvoltages. V D should
not exceed 40 V.
11007a
Vo+/Vo1+
JFET (self-conducting type) to the negative potential of
output 1. V D ≤ 0.4 V (logic low) corresponds to a monitored
voltage level ( V i and/or V o1 ) < V t . The current I D through the
JFET should not exceed 2.5 mA. The JFET is protected by
a 0.5 W Zener diode of 8.2 V against external overvoltages.
NPN open
collector
20
D
I D
R p
V D
11006a
Vo+/Vo1+
I D
R p
14
S–/Vo1–
Self-conducting
junction FET
20
D
V D
Fig. 39
Option D5 – DD: NPN output, V o1 ≤ 40 V, I D ≤ 20 mA
Table 23: JFET output (D5 – DD)
14
S–/Vo1–
Fig. 38
Option D0 – D4: JFET output, I D ≤ 2.5 mA
BCD20001-G Rev AC, 16-Dec-2010
V b , V o1 status
V b or V o1 < V t
V b and V o1 > V t + V h
Page 24 of 29
D output, V D
high, H, I D ≤ 25 μA at V D = 40 V
low, L, V D ≤ 0.4 V at I D = 20 mA
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